Intellectual Property (IP) Core is a logic or data block used to build a Field Programmable Gate Array (FPGA) or Application-Specific Integrated Circuit (ASIC) for a product. In terms of design reuse, IP Cores are an important part of the electronics design industry as they allow pre-designed components to be used repeatedly.
MIL-STD-1553 standard defines three terminal units. These are a bus controller, remote terminal, and bus monitor. The functions of these three terminals have been made software-based using HDL.
The designed 1553 IP Core can be programmed as a Bus controller, Remote terminal, or Bus monitor depending on the user's choice. IP Core is designed to meet the requirements of the MIL-STD-1553B Notice2 standard.
• Operating with 50 MHz clock pulse
• Having a 16-bit long bus to exchange data with the host
• Providing timeout periods defined in the standard
• Ability to detect Manchester and parity errors
• Sending data words to the bus and receiving data words from the bus with its 1Kbit size TxFIFO and RxFIFO
• Error detection and reporting
• Ability to generate commands according to 10 message formats defined in MIL-STD-1553B standard document
• Ability to generate broadcast messages
• Ability to generate all mode commands defined in MIL-STD-1553B standard
• Communication via redundant bus in case of main bus failure
• Re-transmission of erroneous message over same or alternate bus
• Having programmable Remote terminal address (between 0 and 30)
• Receiving broadcast messages traveling on the bus
• Ability to detect illegal commands coming from the data bus
• Supporting Transmit status word, Transmitter shutdown, Override transmitter shutdown, Reset remote terminal and Transmit last command mode commands and generating appropriate response in case of these mode commands
• Ability to generate an automatic status word response by deciphering which message format the command from the data bus is suitable for.
• Ability to communicate over the redundant bus in case of appropriate command from the bus controller
• Receiving data words to be sent to the data bus from the host interface
• Ability to monitor all traffic moving on the bus and save it to its memory elements
• Ability to transmit commands and data words sensed from the data bus to the host interface
• MIL-STD-1553 Terminals
• Sensor Interfaces
• Flight Control System
• 1553 Test Equipment
| Configuration | LUT | FF | BRAM | IO |
| 1BC, 1RT, 1BM | 2015 | 1811 | 0 | 50 |
TRL 9/9
